1. Field of Art
The present invention relates to a control apparatus for controlling a process, such as in a steel-making plant or a petrochemical plant, and particularly, to a control apparatus including an operator provided with processor cores, and subjected to boundary scan tests.
2. Description of Relevant Art
A boundary scan test (sometimes referred herein simply to “JTAG test”) proposed by the JTAG (Joint Test Action Group) was standardized as the IEEE Standard 1149.1-1990, as a method of testing electronics implemented with integrated circuits difficult of a probing board inspection.
The JTAG test will be described with reference to FIG. 11. For the JTAG test, for example, control apparatuses are configured with: a pair of JTAG testers 83 and 84 as testing circuits having target circuits 85 and 86 mounted thereon for their boundary scans; a set of dedicated lines 87 for a daisy chain connection of the JTAG testers 83 and 84; a JTAG controller 82 for driving the JTAG testers 83 and 84 to perform the scans; and a PC (personal computer) 81 provided with a boundary scan control program for controlling the JTAG controller 82.
Typically, the set of dedicated lines 87 includes a pair of signal lines being a TDI (i.e. a signal line connected to a ‘Test Data Input’ terminal) and a TDO (i.e. a signal line connected to a ‘Test Data Output’ terminal) to be connected in series, and a triple of control lines being a TMS (i.e. a signal line connected to a ‘Test Mode Select’ terminal), a TCK (i.e. a signal line connected to a ‘Test ClocK’ terminal), and a TRST (i.e. a signal line connected to a ‘Test ReSeT’ terminal) to be connected in parallel. Such a set of lines is provided as a boundary scan bus.
As illustrated in FIG. 11, signal lines TDI for data to be input and signal lines TDO for data to be output are chained for a serial connection through the JTAG tester 83, target circuit 85, JTAG tester 84, and target circuit 86, starting from and ending on the JTAG controller 82. The control lines are connected in parallel to the target circuits, and serve to control the transfer of input data and output data through the signal lines TDI and TDO.
The JTAG tester 83 has: a set of I/O (input/output) terminals 83a corresponding to I/O pins 83c of the target circuit 85 to be mounted; and a set of boundary scan cells 83b for scanning input data and output data between the set of I/O terminals 83a and the target circuit 85. The JTAG tester 83 is configured to shift a sequence of bits serially output from the JTAG controller 82 as data to be input through a signal line TDI, and whole output data from associated boundary scan cells 83b as data to be output through a signal line TDO.
Likewise, the JTAG tester 84 has: a set of I/O terminals 84a corresponding to I/O pins 84c of the target circuit 86 to be mounted; and a set of boundary scan cells 84b for scanning input data and output data between the set of I/O terminals 84a and the target circuit 86. The JTAG tester 84 is configured to shift a sequence of bits serially output from the JTAG controller 82 as data to be input through a signal line TDI, and whole output data from associated boundary scan cells 84b as data to be output through a signal line TDO.
The JTAG controller 82 follows the boundary scan control program, as it is preset, to transmit serial data to be input through a signal line TDI, receive output data from the target circuits 85 and 86, through a signal line TDO, and compare those output data with preset reference value data, to determine whether or not the output data are conforming.
The I/O terminals 83a and 84a are connected to a normal bus 88 for transmission of input signals and output signals to be processed therethrough in a normal control mode where the target circuits 85 and 86 per se work.
For an improved integrity of electronics provided with such JTAG testers, there have been proposed techniques in which an electronic apparatus per se is configured to function each time when powered on, for an automatic boundary scan to diagnose itself for a normality (refer to patent document 1).
Patent document 1: Japanese Patent Application Laying-Open Publication No. 9-5400
Conventional boundary scan testing devices have been unable to quickly cope with accidental troubles thereon, and some have employed a boundary scan controlling device to have simple boundary scan commands executed for, among others, a startup of a self-testing function to boundary scan compliance ICs on a printed circuit board, or a read-in from specific registers in such IC's (refer to patent document 2).
Patent document 2: Japanese Patent Application Laying-Open Publication No. 2000-206202
On the other hand, in the field of a control apparatus for controlling processes, such as in a steel-making or petrochemical plant, recent years have observed a number of presentations on a control apparatus including a plurality of processor cores (sometimes called a multi-core).
Processor cores constituting the multi-core encompass, among others, a generalized processor core for processing a general-purpose command capable of a programming by software, for example, and a dedicated processor core for processing a specific operation such as for an audio or video, for example.
The former is suitable for implementation of a generic processing, and the latter affords to implement a specific processing with high speed and low power dissipation. This accounts for an increased proportion of a multi-core control apparatus configured with a plurality of processors simply generalized or dedicated, or as a hybrid of generalized or dedicated processors.
The control apparatus is accompanied by an advancing application of reconfigurable devices, e.g. an FGPA (Field Program Gate Array), a PLD (Programmable Logic Device), etc, as hardwares for processor cores to be implemented thereon. The FGPA, PLD, and the like allow for a voluntary reconfiguration of circuitry even after implementation on a substrate, as an advantage.
For occasional increases in number of protocols to be executed or revisions of standards to be complied with, circuit-reconfigurable FGPAs and PLDs have been employed for processor cores dedicated for specific processings, control cores for transmission, and so on.
Control apparatuses provided with such FPGAs or PLDs are subjected to, among others, a trouble shooting of control apparatus, and a renewal of circuitry composed of such devices in control apparatus, whereto an efficient technique using a network has been proposed (refer to patent document 3).
Patent document 3: Japanese Patent Application Laying-Open Publication No. 2001-306343
The patent document 3 has disclosed an apparatus with FPGAs, which has a CPU, a memory, a set of networking elements, and the FPGAs, and is adapted to reconfigure the FPGAs' design data, from a terminal allowed to have an access to the apparatus with FPGAs through a managing apparatus linked by a network.
With a recent trend for a control apparatus to be provided with a plurality of processor cores, there is a tendency for the control apparatus to have an enlarged circuit scale, with an increase in number of I/O pins of integrated circuits constituting processor cores or the like.
Concurrently with the increase in pin number of integrated circuits, micro-fabrication of wiring is advancing in such integrated circuits, as well as on substrates for integrated circuits to be mounted thereon, whereby it is becoming important for a secured integrity of control apparatus to provide functions of, among others, finding defaults due to break or contact failure upon implementation of integrated circuits on substrates, and defective locations in circuitry of the integrated circuits per se, and reconfiguring integrated circuits in trouble.
For such troubles that might be occasional, inspections by in-circuit testers could not afford to quickly cope with, and the control apparatus should be adapted to perform boundary scan tests even in its working state.
For the electronic described in the patent document 1, it is possible to perform boundary scan tests to integrated circuits realizing principal functions of the electronic, to thereby inspect them for a normality. However, there is no provision of a mechanism for inspecting such testing devices per se that are provided to perform the boundary scan tests.
There is thus no way to perform a self-diagnosis for a normality in the boundary scan testing devices, and it is impossible to discriminate whether troubling is a boundary scan testing device or an integrated circuit as a test target, as a problem.
The testing devices are put in a similar environment to integrated circuits, and are subjected to troubles like the integrated circuits. The provision of testing devices thus constitutes an addition of non-testable devices impeding enhancement of integrity of the apparatus, as an issue.
For the printed circuit board described in the patent document 2 also, there is a problem to occur like the patent document 1. That is, although the patent document 2 includes a boundary scan controller of a simplified type adapted to diagnose boundary scan compliance ICs, it is impossible for the printed circuit board to solely diagnose the simplified boundary scan controller itself, as a problem.
For the apparatus with FPGAs described in the patent document 3, it is permitted to receive the FPGAs' design data given via the managing apparatus linked by the network, allowing for a renewal of internal circuits of FPGAs of the apparatus.
However, for the renewal of FPGA circuits, the apparatus with FPGAs should have a renewal processor to implement a renewal processing therein, but is disabled to handle the renewal processor per se as a renewal target, with a necessity for a renewal of design data of the renewal processor itself to provide this renewal processor with another renewal processor, as a problem.